Field of the Invention
The present invention relates to a memory cell configuration having a magnetoresistive memory element, and to a method for producing a memory cell configuration having a magnetoresistive memory element.
In the prior art, the expression magnetoresistive element means a structure which has at least two ferromagnetic layers and a non-magnetic layer disposed in between them. Depending on the construction of the layer structure, a distinction is in this case drawn between a GMR element, a TMR element and a CMR element (see S. Mengel, Technologieanalyse Magnetismus, Band 2, XMR-Technologien, Herausgeber VDI Technologiezentrum Physikalische Technologien [Technological analysis of magnetism, Volume 2, XMR technologies, issued by VDI Technology Center for Physical Technologies], August 1997).
The term GMR element is used for layer structures which have at least two ferromagnetic layers and a non-magnetic, conductive layer disposed in between them and which have what is referred to as a GMR (giant magnetoresistive) effect. The expression GMR effect refers to the fact that the electrical resistance of the GMR element is dependent on whether the magnetization directions in the two ferromagnetic layers are aligned parallel in the same direction or in opposite directions. In comparison to what is referred to as the AMR (anisotropic magnetoresistive) effect, the GMR effect is large. The AMR effect refers to the fact that the resistance in magnetic conductors differs parallel to and at right angles to the magnetization direction. The AMR effect is a volume effect which occurs in single ferromagnetic layers.
In the prior art, the term TMR element is used for tunneling magnetoresistive layer structures, which have at least two ferromagnetic layers and an insulating, non-magnetic layer disposed in between them. The insulating layer is in this case sufficiently thin to allow a tunneling current to flow between the two ferromagnetic layers. These layer structures likewise have a magnetoresistive effect, which is produced by a spin-polarized tunneling current through the insulating, non-magnetic layer disposed between the two ferromagnetic layers. In this case as well, the electrical resistance of the TMR element is dependent on whether the magnetization directions in the two ferromagnetic layers are disposed parallel in the same direction or in opposite directions. The relative resistance change is in this case from approximately 6% to approximately 40%.
A further magnetoresistive effect, which is referred to as the colossal magnetoresistive effect (CMR effect) owing to its magnitude (relative resistance change of 100 to 400% at room temperature) requires a strong magnetic field to switch between the magnetization states, owing to its high coercivity forces.
It has been proposed (see, for example, D. D. Tang et al., IEDM 95, pages 997 to 999, J. M. Daughton, Thin Solid Films, Volume 216 (1992), pages 162 to 168, Z. Wang et al, Journal of Magnetism and Magnetic Materials, Vol. 155 (1996), pages 161 to 163) for GRM elements to be used as memory elements in a memory cell configuration. The memory elements are connected in series via read lines. Word lines run transversely with respect to these read lines and are insulated both from the read lines and from the memory elements. Signals applied to the word lines result in a current flowing in the word line which produces a magnetic field, which influences the memory elements located underneath it, if its intensity is sufficient. Information written using x/y lines, which cross at the memory cell to be written to. Signals are applied to them and cause a magnetic field, which is sufficient for remagnetization, at the crossing point. In the process, the magnetization direction in one of the two ferromagnetic layers is switched. The magnetization direction in the other of the two ferromagnetic layers remains unchanged, however. The fixing of the magnetization direction in the last-mentioned ferromagnetic layer is achieved by using an adjacent antiferromagnetic layer, which fixes the magnetization direction, or by the switching threshold for this ferromagnetic layer being increased by using a different material or different dimensions, for example by increasing the layer thickness in comparison to that of the first-mentioned ferromagnetic layer.
Annular memory elements which are based on the GMR effect have been proposed in U.S. Pat. No. 5,541,868 and U.S. Pat. No. 5,477,483. A memory element including a stack which has at least two annular ferromagnetic layer elements and a nonmagnetic conductive layer element which is disposed between them, and which is connected between two lines. The ferromagnetic layer elements have different material compositions. One of the ferromagnetic layer elements is magnetically hard, and the other is magnetically softer. In order to write information, the magnetization direction in the magnetically softer layer element is switched, while the magnetization direction in the magnetically harder layer element remains unchanged.
With regard to the question as to whether memory cell configurations having magnetoresistive memory elements will become technologically important, one significant factor, among others, is whether such memory cell configurations can be produced using a semiconductor process technique. Neither this problem nor possible solutions have so far been described in the literature.
It is accordingly an object of the invention to provide a memory cell configuration and a method for its production which overcome the hereinafore-mentioned disadvantages of the heretofore-known memory cell configurations and their methods of production of this general type.
The present invention concerns specifying a memory cell configuration having magnetoresistive memory elements which can be produced using a semiconductor process technique, and a method for producing a memory cell configuration having magnetoresistive memory elements using a semiconductor process technique.
This problem is solved by a memory cell configuration having a cell array which has first lines, second lines, and a peripheral area and is disposed in the form of a grid in a first plane; first magnetoresistive memory elements in the cell array disposed between the first lines and the second lines for addressing said magnetoresistive memory elements; at least one first metalization plane, one second metalization plane and contacts in the peripheral area of the cell array, the contacts providing local electrical connections between the first metalization plane and the second metalization plane. The first lines and the first metalization plane are in the same plane for making contact with one another, and the second lines and the contacts are disposed in the same plane.
In one embodiment of the memory cell configuration an intermetal dielectric surrounds the second lines and contacts.
In another embodiment of the memory cell configuration the first lines and the first metalization plane have substantially the same thickness.
In another embodiment of the memory cell configuration the third lines in the cell array and the second metalization plane are in the same plane, and second magnetoresistive memory elements are disposed in a second plane between the second lines and the third lines.
In another embodiment of the memory cell configuration the third lines and the second metalization plane have essentially the same thickness.
In another embodiment of the memory cell configuration the magnetoresistive memory element has a first ferromagnetic layer, a non-magnetic layer and a second ferromagnetic layer, the first ferromagnetic layer and the second ferromagnetic layer contain one of Fe, Ni, Co, Cr, Mn, Gd and Dy and each have a thickness in a range between 2 nm and 20 nm, and the non-magnetic layer contains Al2O3, NiO, HfO2, TiO2, NbO, SiO2, Cu, Au, Ag or Al and has a thickness of between 1 nm and 5 nm.
In another embodiment of the memory cell configuration there is a diffusion barrier between the first lines and the first magnetoresistive memory elements, between the first magnetoresistive memory elements and the second lines, between the second lines and the second magnetoresistive memory elements, and between the second magnetoresistive memory elements and the third lines.
In another embodiment of the memory cell configuration the first lines and the second lines in the cell array contain one of Al, Cu, W and a silicide.
This problem is solved by a method for producing such a memory cell with the following production steps: forming a first line in a cell array on one main surface of a semiconductor substrate by deposition and structuring of a first conductive layer; producing a first metalization plane in a peripheral area; providing first magnetoresistive memory elements in the cell array, each magnetoresistive memory element connected to one of the first lines; forming second lines by depositing and structuring of a second conductive layer in the cell array, the second lines connected to the first magnetoresistive memory elements; forming contacts connected to the first metalization plane in the peripheral area, and forming a second metalization plane by depositing and structuring of a third conductive layer in the peripheral area, the second metalization plane being connected to the contacts.
Another embodiment of the method of producing a memory cell configuration has the additional steps of producing a first insulating layer on the main surface of the semiconductor substrate; producing a first trench in the first insulating layer with a geometric shape corresponding to a geometric shape of the first lines and of the first metalization plane; forming the first lines and the first metalization plane by filling the first trenches with the first conductive layer and planarizing the first trenches for exposing the surface of the first insulating layer; producing a second insulating layer after producing the first magnetoresistive memory elements; forming second trenches having a geometric shape corresponding to a geometric shape of the second lines and of the contacts; filling the second trenches with the second conductive layer, and planarizing the second trenches for exposing a surface of a second insulating layer to form the second lines and the contacts; producing a third insulating layer having third trenches formed therein with a geometric shape corresponding to a geometric shape of a second metalization plane; and filling the third trenches with the third conductive layer and planarizing the third trenches for exposing a surface of the third insulating layer to form the second metalization plane.
Another embodiment of the method of producing a memory cell configuration has the additional steps of forming second magnetoresistive memory elements and connecting each after forming the second lines and the contacts, and connecting each one of the second magnetoresistive memory elements to one of the second lines.
Another embodiment of the method of producing a memory cell configuration has the additional steps of forming second lines and connecting the second lines to the second magnetoresistive elements during the structuring of the third conductive layer in the cell array.
Another embodiment of the method of producing a memory cell configuration has the additional steps of producing a first insulating layer on the main surface of a semiconductor substrate and forming first trenches in the first insulating layer having a geometric shape corresponding to a geometric shape of the first lines and of the first metalization plane; filling and planarizing the first trenches with the first conductive layer for exposing a surface of the first insulating layer to form the first lines and the first metalization plane; producing a second insulating layer after forming the first magnetoresistive elements, and producing second trenches in the second insulating layer having a geometric shape corresponding to a geometric shape of the second lines and of the contacts; filling and planarizing the second trenches with the second conductive layer for exposing a surface of the second insulating layer to form the second lines and the contacts; producing a third insulating layer after forming the second magnetoresistive memory elements, and forming third trenches having a geometric shape corresponding to a geometric shape of the third lines and of the second metalization plane; and filling and planarizing the third trenches with the third conductive layer for exposing a surface of the third insulating layer to form the third line and the second metalization plane.
The memory cell configuration includes a first magnetoresistive memory elements in a cell array, which are disposed in the form of a grid and are each disposed between a first line and a second line. A large number of first lines and second lines are provided. At least one first metalization plane and one second metalization plane are provided in a peripheral area, and are electrically connected to one another via contacts. Such contacts between metalization planes are normally referred to as vias or via connections in the prior art. The contacts are disposed between the first metalization plane and the second metalization plane. The first lines and the first metalization plane are disposed in one and the same plane. The second lines and the second contacts are likewise disposed in one and the same plane. Thus, both the first lines and the first metalization plane as well as the second lines and the contacts may each be produced from a conductive layer by an appropriate structuring.
Since the first lines are disposed in the same plane as the first metalization plane, and the second lines are disposed in the same plane as the contacts, the vertical distance between the first lines and the second lines can be varied independently of the vertical distance between the first metalization plane and the second metalization plane. This has the advantage that the distance between the first lines and the second lines can be matched to the circumstances in the cell array, without affecting the situation in the peripheral area.
As described in the context of the prior art, information is written to one of the magnetoresistive memory elements by applying a magnetic field. The magnetic field is induced by a current flowing through the associated first and second lines. Since the magnitude of the magnetic field depends on the current intensity of the current flowing and on the distance from the conductor through which the current flows, with the magnetic field rising as the current intensity rises and falling as the distance rises, it is desirable to dispose the first lines and the second lines in the vicinity of the magnetoresistive memory elements. Furthermore, it is advantageous to connect each of the magnetoresistive memory elements between two lines since it is then also possible to assess the resistance of the magnetoresistive memory element, which corresponds to the stored information, via these lines. Depending on the thickness of the magnetoresistive memory elements in the cell array, it is desirable to achieve a maximum distance of 20 to 40 nm between first lines and second lines disposed one above the other.
The vertical distance between the first metalization plane and the second metalization plane in the peripheral area must, in contrast, be considerably greater in order to reduce parasitic capacitances between the first metalization plane and the second metalization plane, and for reasons relating to the process. It is typically 350 to 400 nm when using 0.35 xcexcm technology.
The provision of the first lines in the same plane at the first metalization plane, and of the second lines in the same plane as the contacts, thus makes it possible to produce a different distance between the first lines and the second lines in the cell array than in the peripheral area between the first metalization plane and the second metalization plane, so that it is possible to vary the short distance required to achieve low current intensities for writing information by varying the magnetization state of the magnetoresistive element in the cell array, while it is possible to maintain the vertical distance, which is larger by about one order of magnitude, between the metalization planes in the peripheral area as required in terms of parasitic capacitance and technology. At the same time, the first lines and the second lines can be produced together with the structures in the peripheral area. No additional deposition steps, lithography or structuring steps are therefore required for producing the first lines and second lines. The production of the memory cell configuration is thus simplified.
The first lines and the first metalization plane preferably have essentially the same thickness. The second lines and the contacts are surrounded by an intermetal dielectric and terminate essentially at the same level as the intermetal dielectric. This refinement of the invention has a planar surface, which is advantageous in terms of further processing and becomes increasingly important as the structure sizes decrease.
According to a further refinement of the invention, third lines are provided in a cell array, and are disposed above the second lines. Second magnetoresistive memory elements are disposed between the second lines and the third lines, once again with one of the second lines and one of the third lines in each case being associated with one of the second magnetoresistive memory elements. The third lines are disposed in the same plane as the second metalization plane in the peripheral area. In this refinement of the invention, a higher packing density of the memory element is achieved in the cell array, since they are disposed in two planes one above the other. The area required for each memory element thus falls by a factor of 2. In terms of making it easier to drive the cell array, it is in this case advantageous to provide the first magnetoresistive memory elements and the second magnetoresistive memory elements from the same material and with the same characteristics. The characteristics of the first magnetoresistive memory elements and of the second magnetoresistive memory elements may, however, also differ if their application makes this necessary.
Furthermore, it is possible for the memory cell configuration to have further planes with magnetoresistive elements and lines disposed above them, thus resulting in a three-dimensional configuration of the magnetoresistive memory cells with a high packing density. The odd-numbered planes are in this case constructed in an analogous manner to the first lines, the first magnetoresistive elements and the second lines, while the even-numbered planes are constructed analogously to the second lines, the second magnetoresistive elements and the third lines.
With regard to the planarity of the configuration, it is advantageous to provide the third lines and the second metalization plane such that they have essentially the same thickness.
To produce the memory cell configuration, the third lines and the second metalization plane are preferably formed by deposition and structuring of a common, conductive layer.
In order to produce the memory cell configuration with a high level of planarity, it is advantageous to produce the conductive layers (from which the first lines and the first metalization plane, the second lines and the contacts as well as the third lines and the second metalization plane are formed by structuring) by use of planarizing structuring methods. The deposition of insulating layers is particularly suitable for this purpose, in which trenches are produced in the form of the conductive structures which will be produced later, and for these trenches to be filled. Alternatively, the conductive structures can be formed by structuring a conductive layer using lithography and etching methods, with these conductive structures subsequently being surrounded by insulating material, which is structured by deposition and planarization, for example by chemical/mechanical polishing.
The magnetoresistive memory elements each have a first ferromagnetic layer, a non-magnetic layer and a second ferromagnetic layer, with the non-magnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer. The magnetoresistive memory elements can thus be based both on the GMR effect and on the TMR effect. The use of magnetoresistive memory elements which are based on the TMR effect is preferable since the relative resistance change is greater than that with the GMR effect. Furthermore, the higher resistance of the TMR elements is better since the power consumption is lower. In addition, the magnetoresistive memory elements can be based on the CMR effect, provided the configuration can cope with the currents required for switching strong magnetic fields.
The first ferromagnetic layer and the second ferromagnetic layer preferably contain at least one of the elements Fe, Ni, Co, Cr, Mn, Gd, Dy and they have a thickness of between 2 nm and 20 nm. The first ferromagnetic layer and the second ferromagnetic layer have different magnetic hardnesses and/or geometric dimensions.
The non-magnetic layer contains at least one of the materials Al2O3, NiO, HfO2, TiO2, NbO, SiO2, and has a thickness of between 1 nm and 4 nm, when using the TMR effect. For the GMR effect, the non-magnetic layer contains at least one of the materials Cu, Au, Ag and/or Al, and has a thickness of between 2 nm and 5 nm.
The magnetoresistive memory elements have any desired cross section parallel to the line planes. A cross section may, in particular, be rectangular, round, oval, polygonal or annular.
In order to avoid diffusion between the magnetoresistive memory elements and adjacent lines during production and/or operation of the memory cell configuration, it is advantageous to provide a diffusion barrier between each of the magnetoresistive memory elements and the adjacent lines. This effect is particularly important if the lines in the cell array contain Cu, Ag or Au.
Alternatively or additionally, the lines may contain tungsten or metal silicide.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration, and a method for its production, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.